The present invention relates to a semiconductor device manufacturing technology, and particularly to a technique which is effective when applied to a semiconductor device manufacturing technology including the step of, e.g., coupling a semiconductor chip to a base material with metal wires.
Japanese Unexamined Patent Publication No. 2007-214217 (Patent Document 1) discloses a technique which places a belt-like wiring for applying a power source potential or a reference potential (GND potential) around the semiconductor chip mounting region of a wiring board and forms the belt-like wiring with projecting/depressed shapes. According to the technique, the projecting/depressed shapes used in the belt-like wiring are used for positional recognition during wire bonding.
Japanese Unexamined Patent Publication No. 2001-168223 (Patent Document 2) discloses a technique which provides a power source ring with a projecting portion, while providing a GND ring with a depressed portion, and places the power source ring and the GND ring such that the projecting portion and the depressed portion mesh with each other. According to the technique, by configuring the power source ring and the GND ring as described above, a coupling capacitance is increased to allow a reduction in the influence of switching noise.
Japanese Unexamined Patent Publication No. 2004-103720 (Patent Document 3) discloses a structure in which, e.g., wires to be coupled to a GND ring and a power source ring disposed externally of the GND ring are provided within a wiring board, as shown in FIG. 7 of Patent 3.